Nand vs vnand: What’s the difference between NAND and V-NAND? — Answers

Samsung also plans to expand its use of 7th generation V-NAND technology to data center SSDs. In addition, to encourage data center operators to reduce power consumption, Samsung’s solution will feature low power consumption and provide a 16% improvement in energy efficiency over the 6th generation solution.

Today, the company has received a working chip of its 8th generation V-NAND solution with more than 200 cell layers and plans to bring it to market as consumer demand develops.

Samsung V-NAND technology’s grand future: more than 1000 layers

Nothing happens by accident in the semiconductor industry. The development of a previously unknown technology requires not only time, but also huge investments and capital investments. Samsung has been able to become a world leader in the semiconductor industry despite setbacks and other challenges, and has managed to maintain the enthusiasm, attitude and sense of duty that allows us to achieve a better life for all those who need such innovations.

Just like the first generation of V-NAND introduced in 2013 after more than ten years of research, the company will be the first to overcome the height limitations that the industry has yet to face and succeed thanks to its 3D zoom technology. Even in the future, when Samsung V-NAND solutions will consist of more than 1000 layers, the company will continue to ensure that its memory chips are the most reliable in the industry.

New Augmented Reality Paradigm Empowers Semiconductors

Today, the world is moving towards a new Augmented Reality (XR) paradigm made possible by the rapid development of technology. In fact, the pandemic has greatly accelerated the adoption of XR technologies in our daily lives, and a new era is dawning where reality and cyberspace intersect. Moreover, the improvement of IT devices and technologies will require a completely new approach that will be completely different from anything we have seen before, with the role of semiconductors becoming more important than ever before.

Undoubtedly, Samsung will continue its work to improve society and introduce innovative semiconductor products based on powerful technological advances. Thus, you can be sure that the precious memories stored on your electronic devices will last for a very long time.

3D NAND flash memory technology / Sudo Null IT News

Hello everyone! As you know, modern planar NAND flash memory has almost exhausted its potential. Its main problem is that it is becoming increasingly difficult to reduce the size of the crystal. Experts predict that 14-15 nm technological standards will become the limit of planar flash memory, at least for the near future. And it will be replaced by the technology of «vertical» flash memory — 3D NAND.

It is very important to understand what prevents a further reduction in the size of the crystal. First of all, the development of finer technical processes requires expensive equipment, the purchase of which may not be justified from an economic point of view in the future. And if the acquisition of new lithographic machines is a solvable issue, then the problem of charge flow from one cell to another, due to which errors occur, is not so easy to solve.

In a word, the industry found itself in a situation where the resources of conventional, planar, flash memory were exhausted. Therefore, the idea arose to place cells not only in a plane, but also in layers. Thus, the chip receives a three-dimensional structure and is able to contain much more information per unit area than two-dimensional crystals. The technology is called 3D NAND. It is also worth noting here that manufacturers use different techniques to create three-dimensional memory, so the 3D NAND architecture of each company may have its own characteristics and differences.

The first company to start producing 3D flash memory called 3D V-NAND and drives based on them was the Korean giant Samsung. Back in 2013, they announced the release of the first 3D MLC chips with 24 layers. A year later, TLC flash memory received 3D implementation, the number of layers of which increased to 32.

As you know, the design of planar flash memory is based on a floating gate transistor. The floating gate has the ability to hold a charge for a long time. As it turned out, this is the main drawback of the design: with a decrease in the technical process due to cell wear, the charge can flow from one cell to another. To solve this problem, Samsung uses 3D Charge Trap Flash technology, which means «charge trap» in English.

Its essence lies in the fact that the charge is now placed not in a floating gate, but in an isolated region of a cell made of a non-conductive material, in this case silicon nitride (SiN). This reduces the likelihood of «leakage» of the charge and increases the reliability of the cells.

Among other things, the use of CTF technology has made memory chips more economical. According to Samsung, savings can be as high as 40% compared to planar memory.

A three-dimensional 3D V-NAND cell is a cylinder, the outer layer of which is a control gate, and the inner layer is an insulator. The cells are located one above the other and form a stack, inside which a cylindrical channel made of polycrystalline silicon passes common to all cells. The number of cells in the stack is equivalent to the number of layers of flash memory.

3D V-NAND memory also boasts faster performance. This was achieved by simplifying the algorithm for writing to a cell — now, instead of three operations, only one is performed. The simplification of the algorithm became possible due to less interference between cells. In the case of planar memory, due to possible interference between neighboring cells, additional analysis was required before recording. Vertical memory is free from this problem and writing is done in one step.

Well, a few words about reliability. 3D V-NAND memory is much less subject to wear and tear due to the fact that high voltage is not required to write information to the cell. Recall that in order to place data in a planar memory cell, a voltage of about 20 V is used. For three-dimensional memory, this figure is lower. Reliability was also favorably affected by the fact that the production of three-dimensional flash memory does not require fine technological standards. For example, the third generation of 3D V-NAND memory with 48 layers is manufactured using a well-established 40 nm process technology.

While Samsung was producing 3D flash memory chips at a loss (which, by the way, was officially confirmed by a Korean company), other flash memory manufacturers were developing competing technologies. So, Toshiba and SanDisk have teamed up in an alliance to release a three-dimensional flash memory BiCS 3D NAND (Bit Cost Scalable).

Work on the technology began back in 2007 by Toshiba alone, and the first samples of BiCS 3D flash memory were demonstrated in 2009year. Since then, the development of technology has not been accelerated. In addition, the Toshiba/SanDisk alliance has made it clear that they are not going to mass-produce 3D flash memory until it is economically viable.

The main difference between Toshiba’s 3D flash memory and planar, as in the case of Samsung 3D V-NAND, is the use of CTF technology instead of classic floating gate transistors. The material for the isolated region is also silicon nitride (SiN). The principle of operation of the technology in BiCS 3D NAND remains the same: the information is not placed in a floating gate, as before, but in an isolated area.

What distinguishes BiCS 3D NAND from 3D V-NAND technology is the use of U-shaped strings (lines). This means that the cells are not grouped in a row, but in a U-shaped sequence. According to Toshiba, this approach allows for maximum reliability and speed. This is possible because the U-shaped design places the switching transistor and the source line at the top of the sequence (rather than at the bottom of the «in-line» design) and is not exposed to high temperatures, thereby reducing read and write errors. .

Another advantage of Toshiba’s U-shaped design is the fact that this design does not require the use of deep ultraviolet photolithography. Therefore, the company can use existing production facilities to manufacture 3D flash memory.

It is also interesting that in the production of BiCS 3D NAND, Toshiba will be the first to use thin-film transistor (TFT) technology in mass production.

As for the technical characteristics of BiCS chips, these will be 48-layer TLC-type memory chips. Their density will be 256 Gbps. The production will use a debugged 30-40 nm process technology. In general, the characteristics of the first mass-produced BiCS 3D NAND chips will be very similar to the third generation of Samsung 3D V-NAND chips.

The Micron/Intel alliance is also developing its own 3D flash memory. Many experts predicted that all 3D NAND projects would use CFT technology, but Micron and Intel surprised everyone and went the other way. The basis of their 3D flash memory is floating gate cells. Micron claims that it is this architecture that allows more reliable storage of charge in the cell.

In addition, 3D NAND technology uses «CMOS Under the Array» technology. Its meaning is that all control logic is placed not next to the memory array, as in 2D NAND, but under it. Such a design allows freeing up to 20% of the chip area and placing memory cells in this place.

Micron promises to mass-produce 3D flash memory chips this year. These will be 32-layer crystals with a density of 256 Gb (MLC) and 384 Gb (TLC).

Not much is known about the architecture of SK Hynix 3D flash memory. Initially, the South Korean company planned to use floating gate cells, but in the end the choice fell on CTF technology. This year, SK Hynix promises to finally mass-produce 3D NAND. These will be 48-layer TLC chips with a capacity of 256 Gbps.